The Memory Wars — Life in a Zero-Sum World: IRQ Conflicts — When Programs Collide

There are only fifteen interrupts, and every device believes it deserves one. This is the origin of all war.

The IBM PC architecture provides fifteen usable hardware interrupt request lines, numbered IRQ 0 through IRQ 15, with IRQ 2 cascaded to the secondary interrupt controller and therefore not truly available — a bureaucratic subtlety that has caused more suffering than any intentional cruelty in the history of computing. Each IRQ is a wire, a physical conductor on the ISA bus, and when a hardware device asserts its IRQ line, the programmable interrupt controller (the 8259A, a chip whose patience is legendary) signals the CPU to stop whatever it is doing and service the interrupt. The system is elegant. The system is also, in practice, a nightmare. The problem is scarcity. IRQ 0 belongs to the system timer. IRQ 1 belongs to the keyboard. IRQ 6 belongs to the floppy controller. IRQ 14 belongs to the primary hard disk. These assignments are non-negotiable, hardwired into the BIOS like the laws of thermodynamics. What remains — IRQ 3, 4, 5, 7, 9, 10, 11, 12, 15 — must be shared among every e...

From the lore of Conventional Memory.